View PCS1P2192A_4945425.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

June 2009 rev 1.0 VDP Multiple Pixel Clock Generator
Features
* Generates multiple clock outputs from 20MHz
PCS1P2192A
Product Description
The PCS1P2192A is a clock generator that generates multiple selectable pixel clock outputs for Video Display Panel applications from an external 20MHz reference clock. The PLL based clock generator is specifically designed to provide zero ppm frequency synthesis error on all clock outputs. Various pixel clock rates are selectable through frequency selection pins S[2:0] (Refer Frequency Selection Table) The device provides a reference clock output additionally. Operating Supply Voltage for this device is 3.3V 0.3V. The device is available in an 8 pin SOIC package, in commercial temperature grade.
external reference clock
* Input frequency: 20MHz * Output frequencies: *
Selectable CLKOUT: 108MHz, 27MHz, 33.2MHz, 85MHz, 65MHz, 25MHz, 45MHz, and 40MHz
*
REFOUT: 20MHz
* Operating Supply Voltage: 3.3V 0.3V * Zero ppm frequency synthesis error on all clock
outputs
* Commercial temperature: 0C to +85C * 8-pin SOIC package
Applications
PCS1P2192A is targeted towards Video Display Panel (VDP) applications like VGA, SVGA, XGA, WXGA, UXGA.
Block Diagram
VDD
[S2: S0]
CLKIN
PLL
CLKOUT
REFOUT
GND
PulseCore Semiconductor Corporation 2105 S. Bascom Ave Suite 210, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
June 2009 rev 1.0
Pin Configuration
PCS1P2192A
CLKIN
1
8 7
VDD CLKOUT REFOUT S2
GND 2 PCS1P2192A S0 3 S1 4
6 5
Pin Description Pin#
1 2 3 4 5 6 7 8
Pin Name
CLKIN GND S0 S1 S2 REFOUT CLKOUT VDD
Type
I P I I I O O P
Description
20MHz external reference clock input. Ground Connection. Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer Frequency Selection Table) Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer Frequency Selection Table) Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer Frequency Selection Table) Reference clock output Clock output Device Power Supply
Frequency Selection Table S2
0 0 0 0 1 1 1 1
S1
0 0 1 1 0 0 1 1
S0
0 1 0 1 0 1 0 1
CLKOUT (MHz)
108 27 33.2 85 65 25 45 40
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
2 of 8
June 2009 rev 1.0
Absolute Maximum Ratings Symbol
VDD, VIN TSTG Ts TJ TDV Storage temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B)
PCS1P2192A
Parameter
Voltage on any input pin with respect to Ground
Rating
-0.5 to +4.6 -65 to +125 260 150 2
Unit
V C C C KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Recommended Operating Conditions Parameter
VDD TA CL CIN Operating Voltage Operating Temperature Load Capacitance Input Capacitance
Description
Min
3.0 0
Typ
3.3
Max
3.6 +85 15 7
Unit
V C pF pF
DC Electrical Characteristics Symbol
VIL VIH IIL IIH VOL VOH IDD ICC VDD tON ZOUT
Parameter
Input low voltage (For CLKIN) Input high voltage (For CLKIN) Input low current Input high current Output low voltage (VDD = 3.3V, IOL = 8mA) Output high voltage (VDD = 3.3V, IOH = -8mA) Static supply current * Dynamic supply current (3.3V and no load) Operating Voltage Power-up time (first locked cycle after power-up) Output impedance
Min
GND - 0.3 2.0
Typ
Max
0.8 VDD + 0.3 50 -50 0.4
Unit
V V A A V V mA mA V mS
2.4 5 9 3.0 3.3 1 40 3.6
* CLKIN pulled low
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
3 of 8
June 2009 rev 1.0
AC Electrical Characteristics Symbol
fIN fOUT tLH* tHL* tJC tD Input frequency Output frequency Output rise time ( Measured from 20% to 80% ) Output fall time ( Measured from 80% to 20% ) Period Jitter Frequency Synthesis Error (All Outputs) Output duty cycle 40 1.2 0.8 150 0 50
PCS1P2192A
Parameter
Min
Typ
20 108, 27, 33.2, 85, 65, 25, 45, 40
Max
Unit
MHz MHz
2.5 1.6
nS nS pS ppm
60
%
* measured with a capacitive load of 15pF
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
4 of 8
June 2009 rev 1.0
Typical Application Schematic
VDD CLKIN
PCS1P2192A
1 2
CLKIN GND
VDD
8 0.01uF GND
VDD 0 0 VDD 0
CLKOUT 7
3
S0
REF 6
VDD 0
4 0
S1
S2
5 0
Use either pull-up or pull-down 0 Resistor with [S2:S0] for selection of CLKOUT frequencies
PCB Layout Recommendation For optimum device performance, following guidelines are recommended. * Dedicated VDD and GND planes. * The device must be isolated from system power supply noise. A 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible. All the VDD pins should have decoupling capacitors. * In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers. A typical layout is shown in the figure
As short as possible
VDD GND
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
5 of 8
June 2009 rev 1.0
Package Information
PCS1P2192A
8-Pin SOIC Package
E
H
D
A2
A
e B A 1
C L
D
Dimensions Symbol
A1 A A2 B C D E e H L
Inches Min Max
0.004 0.053 0.049 0.012 0.007 0.010 0.069 0.059 0.020 0.010
Millimeters
Min
0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0
Max
0.25 1.75 1.50 0.51 0.25
0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.050 8
1.27 8
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
6 of 8
June 2009 rev 1.0
Ordering Code Part Number
PCS1P2192AG-08ST PCS1P2192AG-08SR
PCS1P2192A
Marking
PCS 1P2192AG PCS 1P2192AG
Package Type
8-Pin SOIC, TUBE, Green 8-Pin SOIC, TAPE & REEL, Green
Temperature *
Commercial Commercial
*VDP commercial temperature range (0C to +85C)
Device Ordering Information
PCS1P2192AG-08SR
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
PulseCore Semiconductor Mixed Signal Product
Licensed under U.S Patent Nos 5,488,627 and 5,631,921
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
7 of 8
June 2009 rev 1.0
PCS1P2192A
PulseCore Semiconductor Corporation 2105 S. Bascom Ave Suite 210 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Part Number: PCS1P2192A Document Version: 1.0
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Many PulseCore Semiconductor products are protected by issued patents or by applications for patent
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
8 of 8

▲Up To Search▲

Price & Availability of PCS1P2192A

	To Download PCS1P2192A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .